1. Field of the Invention
The present invention is related to a method for variation detection; in particular, to a method for detecting variation in semiconductor processes, which performs correlation analyses on huge amount and complicated raw data outputted by semiconductor process tools to facilitate engineers to locate the sources generating such process variations.
2. Description of Related Art
Yield is a very important index in semiconductor manufactories; on one hand, yield indicates the success rate of producing wafer of a semiconductor manufacturer; on the other hand, yield also is crucially related with the potential profit of a semiconductor manufacturer. Therefore, how to enhance the yield has become one momentous issue of attention to which most semiconductor manufacturers closely and prudently pay.
Regarding this point, semiconductor manufacturers in recent years have devoted great efforts in researches and developments on Metrology integrated system technology and automatic real-time monitoring system, which monitors semiconductor process tools in order to increase wafer production yield and reduce occurrences of risks. The mostly employed system technology and automatic real-time monitoring system in current semiconductor manufacturers is the Fault Detection and Classification (FDC), used to analyze outputted data by the semiconductor tools to appreciate the causes of flaws occurred in wafers, further taking actions thereon beforehand so as to achieve the objectives about wafer yield enhancement, while avoiding wastes of massive and precious time and manpower resources on trouble-shooting.
For example, in Republic of China Patent Application No. 093118756, entitled “Method and System for Semiconductor Tools Yield Correlation Analysis and Method of Semiconductor Manufacturing implemented thereby and Storage Media for Storing Computer Application for Execution of the Method”, discloses a method for semiconductor tools yield correlation analysis using a computer system to execute the following steps: initially, selecting the required analysis on yield record data of at least one wafer, and having the yield data inputted; next, performing statistics on the frequency of passing through a semiconductor tool of the wafer during a process, accordingly generating a frequency diagram; then, generating a p-test diagram based on the yield record data; and subsequently, generating a high percentage group and a low percentage group in accordance with a percentage limit value, calculating the high percentage group and the low percentage group to generate an abnormal analysis result; and further, based on an abnormal critical value, comparing the calculated abnormal analysis result with the abnormal critical value to analyze whether said semiconductor tool is normal; finally, detecting said semiconductor tool according to the calculated analysis results. The method is depicted in FIG. 1. However, in terms of the correlation of the machine, the aforementioned patent can only be applied in detection single semiconductor or single process step, and cannot be applied in multiple process steps to analyze the influence on yield of a plurality of semiconductor process tools. Therefore, in, terms of most monitoring methods or equipments, said Patent is unable to effectively locate the semiconductor tool among many which affects the yield the most in multiple process steps.
Furthermore, in Republic of China Patent Application No. 091138167, titled “Method for Flaw Detection Parameter Analysis”, said Patent discloses a method for flaw detection parameter analysis (refer to FIG. 2), which is used to analyze plural batches of products, each having a batch number, each product being fabricated by means of a plurality of tools, and one or more wafers in each batch of products having been examined through at least one flaw detection item to generate a flaw detection parameter value; engineers may accordingly determine which process has problems and leads to the reduction in wafer yield, based on the information of the flaw detection parameter value; however, the method used in the aforementioned patent application is excessively complicated and engineers need to set various rules to perform flaw detection analysis; hence much time is spent in rule setting, causing unnecessary wastes of precious resources, leading to insufficiency in practical usage.
Accordingly, having considered the above-mentioned amendable detects, the present inventors proposed the present invention for providing reasonable and effective improvement on the disadvantages described supra.